sample	condition
D.S101_S1	100k_tex_d4
D.S102_S12	100k_tex_d4
D.S103_S23	100k_teff_d4
D.S105_S40	100k_tex_d4
D.S106_S41	100k_tex_d4
D.S107_S42	100k_teff_d4
D.S108_S43	100k_teff_d4
D.S117_S9	100k_tex_d7
D.S118_S10	100k_tex_d7
D.S119_S11	100k_teff_d7
D.S120_S13	100k_teff_d7
D.S121_S14	100k_tex_d7
D.S122_S15	100k_tex_d7
D.S123_S16	100k_teff_d7
D.S124_S17	100k_teff_d7
D.S133_S27	naive
D.S134_S28	naive
D.S136_S30	naive